1. Field of the Invention
The invention relates to a method involving patterned photoresist, or other adhesive material, for bonding substrates together.
2. Discussion of the Background
Conventional packaged microelectronic devices include a singulated microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame, and supply voltage, signals, etc., are transmitted to and from the integrated circuit via the bond-pads. In addition to the terminals, the interposer substrate can also include ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.
Packaged microelectronic devices such as those described above are used in cellphones, pagers, personal digital assistants, computers, and many other electronic products. To meet the demand for smaller electronic products, there is a continuing drive to increase the performance of packaged microelectronic devices, while at the same time reducing the height and the surface area or “footprint” of such devices on printed circuit boards. Reducing the size of high performance devices, however, is difficult because the sophisticated integrated circuitry requires more bond-pads, which results in larger ball-grid arrays and thus larger footprints. One technique for increasing the component density of microelectronic devices within a given footprint is to stack one device on top of another.
Formation of 3D metal interconnects on stacked IC chips has generally been accomplished using one of the two approaches: 1) Vias-First—interconnect formed before IC fabrication/thinning/bonding, or 2) Vias-Last—interconnect formed after IC fabrication/thinning/bonding
The Vias-Last approach invariably requires some type of bottom clear etching of the via. FIG. 1 shows one example of a vias last approach using an un-patterned adhesive.
The difficulty of the bottom clear etch in step (3) depicted in FIG. 1 generally increases with the thickness of materials to be etched, and increases with the aspect ratio of the via. In many cases, bottom clear etches may also require an etch mask, contributing process complexity and integration issues.
The present invention addresses these and other difficulties in the Vias-Last approach while permitting via formation prior to bonding.